1. Field of the Invention
The invention relates to a semiconductor device having a metal gate and manufacturing method thereof, and more particularly, to a semiconductor device having a metal gate and manufacturing method applied with a gate last process.
2. Description of the Prior Art
Polysilicon is conventionally used as gate electrode in the semiconductor device, such as the metal-oxide-semiconductor (MOS). However, with a trend toward scaling down the size of the semiconductor device, the conventional polysilicon gate has faced problems such as inferior performance due to boron penetration and unavoidable depletion effect which increases equivalent thickness of the gate dielectric layer, reduces gate capacitance, and worsens a driving force of the devices. Therefore, work function metals are used to replace the conventional polysilicon gate to be the control electrode that competent to the high-K gate dielectric layer.
In a complementary metal-oxide semiconductor (CMOS) device, one of the dual work function metal gates is used in an NMOS device and the other one is alternatively used in a PMOS device. It is well-known that compatibility and process control for the dual metal gate are more complicated, meanwhile thickness and composition controls for materials used in the dual metal gate method are more precise. The conventional dual metal gate methods are categorized into gate first process and gate last process. In a conventional dual metal gate method applied with the gate first process, the anneal process for forming the source/drain ultra-shallow junction, and the silicide process are performed after forming the metal gate. After the anneal process having such strict heat budget, it is found that a flat band voltage (Vfb) does not increase or decrease linearly with decrease of EOT of the high-K gate dielectric layer. Instead, a roll-off issue is observed. Therefore, the gate last process is developed to improve the Vfb roll-off issue and avoid generating leakage current due to re-crystallization of the high-K gate dielectric layer happened in high-temperature processes, and to widen material choices for the high-K gate dielectric layer and the metal gate in the gate first process.
In the conventional gate last process, a dummy gate or a replacement gate is provided and followed by performing processes used to construct a normal MOS transistor. Then, the dummy/replacement gate is removed to form a gate trench. Consequently, the gate trench is filled with metals according to the different electrical requirement. It is found that the gate last process is able to avoid processes of high thermal budget and to provide wider material choices for the high-K gate dielectric layer and the metal gate. However, the gate last process still faces integrity requirements for the complicated processes and reliability requirement for the gate trench filling.